Semiconductor Device and Method of Fabricating the Same

ABSTRACT

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom suffice of the first trench.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.14/924,217, filed Oct. 27, 2015, which itself claims priority fromKorean Patent Application No. 10-2014,-0151278 filed on Nov. 3, 2014 inthe Korean Intellectual Property Office, and all the benefits accruingtherefrom under 35 U.S.C. 119, the contents of which in their entiretiesare herein incorporated by reference.

TECHNICAL FIELD

The present inventive concept relates to a semiconductor device and amethod of fabricating the same, and, more particularly, to asemiconductor device including a copper wire and a method of fabricatingthe same.

BACKGROUND

With development of electronic technology, and as down-scaling of asemiconductor device has rapidly progressed in recent years,high-integration and low-power of a semiconductor chip have beenrequired.

To meet the high-integration and lower power goals, semiconductordevices have been fabricated with improvements in wire resistance andelectromigration resistance. Copper, which is relatively high inconductivity and high in resistance to electromigration, may be used asa wire material.

SUMMARY

Embodiments according to the present inventive concept may provide asemiconductor device of which reliability can be enhanced by improvingelectromigration resistance of a metal wire through controlling the topshape of the metal wire.

Embodiments according to the present inventive concept may also providea method of fabricating a semiconductor device of which reliability canbe enhanced by improving electromigration resistance of a metal wirethrough controlling the top shape of the metal wire.

According to an aspect of the present inventive concept, there isprovided a semiconductor device comprising a first interlayer insulatinglayer including a first trench, on a substrate a first liner layerfanned along a side wall and a bottom surface of the first trench andincluding noble metal, the noble metal belonging to one of a fifthperiod and a sixth period of a periodic chart that follows numbering ofInternational Union of Pure and Applied Chemistry (IUPAC) and belongingto one of eighth to tenth groups of the periodic chart, and a firstmetal wire filling the first trench on the first liner layer, a topsurface of the first metal wire having a convex shape toward a bottomsurface of the first trench.

In some embodiments of the present inventive concept, at a point wherethe first liner layer and the top surface of the first metal wire areadjacent to each other, an uppermost surface of the first liner layerand the top surface of the first metal wire are continuous.

In some embodiments of the present inventive concept, at the point wherethe first liner layer and the top surface of the first metal wire areadjacent to each other, no step is formed between the uppermost surfaceof the first liner layer and the top surface of the first metal wire.

In some embodiments of the present inventive concept, the uppermostsurface of the first liner layer and the top surface of the first metalwire directly contact each other.

In some embodiments of the present inventive concept, the top surface ofthe first metal wire does not protrude above the uppermost surface ofthe first liner layer on the whole.

In some embodiments of the present inventive concept, the top surface ofthe first metal wire comprises a first point and a second point, adistance up to the first point from a point where the top surface of thefirst metal wire and the uppermost surface of the first liner layer meetis less than a distance up to the second point from the point where thetop surface of the first metal wire and the uppermost surface of thefirst liner layer meet, and a depth up to the first point from theuppermost surface of the first liner layer is less than a depth up tothe second point from the uppermost surface of the first liner layer.

In some embodiments of the present inventive concept, the noble metalcomprises at least one of ruthenium (Ru), platinum (Pt), iridium (Ir),and rhodium (Rh).

In some embodiments of the present inventive concept, the first linerlayer is conformally formed along the side wall and the bottom surfaceof the first trench.

In some embodiments of the present inventive concept, a thickness of thefirst liner layer formed on the bottom surface of the first trench isgreater than the thickness of the first liner layer formed on the sidewall of the first trench.

In some embodiments of the present inventive concept, the first linerlayer formed on the side wall of the first trench has an overhangstructure, at a portion where the top surface of the first metal wireand the uppermost surface of the first liner layer meet.

In some embodiments of the present inventive concept, the semiconductordevice may further comprise a capping layer formed on the top surface ofthe first metal wire.

In some embodiments of the present inventive concept, the capping layerdirectly contacts the first liner layer and the first metal wire.

In some embodiments of the present inventive concept, the capping layercovers the top surface of the first metal wire.

In some embodiments of the present inventive concept, the capping layerextends onto the uppermost surface of the first liner layer.

In some embodiments of the present inventive concept, the capping layerdoes not extend on the top surface of the first interlayer insulatinglayer.

In some embodiments of the present inventive concept, the capping layerincludes a portion that protrudes above the uppermost surface of thefirst liner layer.

In some embodiments of the present inventive concept, the capping layercomprises at least one of cobalt (Co), ruthenium (Ru), and manganese(Mn).

In some embodiments of the present inventive concept, the semiconductordevice may further comprise a first barrier layer formed along the sidewall and the bottom surface of the first trench, between the firstinterlayer insulating layer and the first liner layer.

In some embodiments of the present inventive concept, the semiconductordevice may further comprise a capping layer formed on the top surface ofthe first metal wire. The capping layer extends onto the uppermostsurface of the first barrier layer.

In some embodiments of the present inventive concept, the first metalwire comprises copper (Cu).

In some embodiments of the present inventive concept, the semiconductordevice may further comprise a second interlayer insulating layercomprising a second trench, on the first interlayer insulating layer, asecond liner layer formed along a side wall and a bottom surface of thesecond trench and including the noble metal, and a second metal wirefilling the second trench and electrically connected with the firstmetal wire. A top surface of the second metal wire has a convex shapetoward the bottom surface of the second trench.

In some embodiments of the present inventive concept, the semiconductordevice may further comprise a second barrier layer formed along the sidewall and the bottom surface of the second trench, between the secondinterlayer insulating layer and the second liner layer.

In some embodiments of the present inventive concept, the second barrierlayer formed On the bottom surface, of the second trench is formed alonga profile of the top surface of the first metal wire.

In some embodiments of the present inventive concept, the second barrierlayer directly contacts the first metal wire.

In some embodiments of the present inventive concept, the semiconductordevice may further comprise a capping layer formed on the top surface ofthe first metal wire. The capping layer is disposed between the topsurface of the first metal wire and the second liner layer formed on thebottom surface of the second trench.

According to another aspect of the present inventive concept, there isprovided a semiconductor device comprising an interlayer insulatinglayer including a trench, on a substrate, first liner layer formed alonga side wait and a bottom surface of the trench, a metal wire filling thetrench and comprising copper (Cu), on the first liner layer, a topsurface of the metal wire having a convex shape toward the bottomsurface of the trench, and a second liner layer including a first partformed along the side wall and the bottom surface of the metal wire anda second part formed along the top surface of the metal wire, the secondliner and covering the metal wire, wherein any one of the first linerlayer and the second liner layer comprises a noble metal that belongs toone of a fifth period and a sixth period of a periodic chart thatfollows numbering of International Union of Pure and Applied Chemistry(IUPA) and belongs to one of eighth to tenth groups of the periodicchart.

In some embodiments of the present inventive concept, the first part ofthe second liner layer is disposed between the first liner layer and themetal wire, and the noble metal is in the first part of the second linerlayer.

In some embodiments of the present inventive concept, the first part ofthe second liner layer directly contacts the metal wire, and no step isformed between an uppermost surface of the first part of the secondliner layer and the top surface of the metal wire.

In some embodiments of the present inventive concept, the second part ofthe liner layer does not extend onto an uppermost surface of the firstliner layer.

In some embodiments of the present inventive concept, the first linerlayer is disposed between the first part of the second liner layer andthe metal wire, and the noble metal is in the first liner layer.

In some embodiments of the present inventive concept, the first linerlayer and the metal wire directly contact each other, and no step isformed between the uppermost surface of the first liner layer and thetop surface of the metal wire.

In some embodiments of the present inventive concept, the second part ofthe liner layer does not extend onto a top surface of the interlayerinsulating layer.

In some embodiments of the present inventive concept, the second part ofthe second liner layer comprises at least one of cobalt (Co), ruthenium(Ru) and manganese (Mn).

According to still another aspect of the present inventive concept,there is provided a semiconductor device comprising an interlayerinsulating layer comprising a trench, on a substrate, a barrier layerformed along a side wall and a bottom surface of the trench a ruthenium(Ru) liner layer formed along the side wall and the bottom surface ofthe trench, on the barrier layer, a metal wire filling the trench andcomprising copper, on the ruthenium liner layer, a top surface of themetal wire having a convex shape toward the bottom surface of the trenchand being continuous with an uppermost surface of the ruthenium linerlayer, and a capping layer formed along the top surface of the metalwire.

In some embodiments of the present inventive concept, the metal wiredirectly contacts the liner layer, and no step is formed between theuppermost surface of the liner layer and the top surface of the metalwire.

In some embodiments of the present inventive concept, the capping layeris a cobalt (Co) laver.

In some embodiments of the present inventive concept, the barrier layercomprises tantalum (Ta).

In some embodiments of the present inventive concept, the capping layerdoes not extend on a top surface of the interlayer insulating layer.

In some embodiments of the present inventive concept, the interlayerinsulating layer comprises a low-dielectric material having a lowerdielectric constant than silicon oxide.

According to still another aspect of the present inventive concept,there is provided a semiconductor device comprising an interlayerinsulating layer including a trench, on a substrate, a barrier layerformed along a side wall and a bottom surface of the trench, a linerlayer formed along the side wall and the bottom surface of the trench,on the harrier layer; and a metal wire filling the trench and comprisingcopper, on the liner layer, a top surface of the metal wire being acurved surface, and being continuous with an uppermost surface of theliner layer, and not protruding above a top surface of the interlayerinsulating layer, wherein a wetting angle having copper in a reflowstate on the liner layer is a first angle, and the wetting angle havingthe copper in the ram state on the barrier layer is a second angle, andthe second angle is greater than the first angle.

In some embodiments of the present inventive concept, the first angle isan acute angle and the second angle is an obtuse angle.

In some embodiments of the present inventive concept, the liner layerincludes metal that belongs to one of a fifth period and a sixth periodof a periodic char that follows numbering of international Union of Pureand Applied Chemistry (IUPAC) and belongs to one of eighth to tenthgroups of the periodic chart,

In some embodiments of the present inventive concept, the liner layercomprises at least one of ruthenium (Ru), platinum (Pt), iridium (Ir),and rhodium (Rh).

In some embodiments of the present inventive concept, the barrier layercomprises at least one of tantalum (Ta) and titanium (Ti).

According to still another aspect of the present inventive concept,there is provided a semiconductor device comprising a metal wireextending in one direction on a substrate, a top surface of the metalwire having a half-pipe shape, a ruthenium liner layer formed along, aside wall and a bottom surface of the metal wire, a capping layer formedalong the top surface of the metal wire, a via formed on the metal wire,and a barrier layer disposed between a bottom surface of the via and thetop surface of the metal wire.

In some embodiments of the present inventive concept, the barrier layerdirectly contacts the capping layer.

In sonic embodiments of the present inventive concept, the capping layercomprises an opening that exposes the top surface of the metal wire, andthe barrier layer directly contacts the metal wire through the opening.

According to still another aspect of the present inventive concept,there is provided a method of fabricating a semiconductor devicecomprising forming an interlayer insulating layer including a trench,forming a prebarrier layer and a preliner layer comprising rutheniumsequentially along a side wall and a bottom surface of the trench, and atop surface of the interlayer insulating layer, forming a metal layerfilling the trench and covering the top surface of the interlayerinsulating layer, on the preliner layer, forming a metal wire in thetrench by exposing the top surface of the interlayer insulating layer byusing a planarization process, and forming a capping layer on a topsurface of the metal wire, wherein the top surface of the metal wire hasa convex shape toward the bottom surface of the trench.

In some embodiments of the present inventive concept, the preliner layeris formed by using chemical, vapor deposition.

In some embodiments of the present inventive concept, the capping layeris formed by selectively depositing a layer on the top surface of themetal wire, and the capping layer does not extend onto a top surface ofthe interlayer insulating layer.

In some embodiments of the present inventive concept, the forming of themetal layer comprises forming a pre-metal layer on the top surface ofthe interlayer insulating layer and in the trench, and reflowing thepre-metal layer.

In some embodiments of the present inventive concept, the metal layer isformed by using an electroplating method.

Other methods, systems, and/or devices according to embodiments of theinventive subject matter will be or become apparent to one with skill inthe art upon review of the following drawings and detailed description.It is intended that all such additional methods, systems, and/or devicesbe included within this description, be within the scope of the presentinventive concepts, and be protected by the accompanying claims.Moreover, it is intended that all embodiments disclosed herein can beimplemented separately or combined in any way and/or combination.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventiveconcept will become more apparent by describing in detail embodimentsthereof with reference to the attached drawings in which:

FIG. 1 is a diagram for illustrating a semiconductor device according tosome embodiments of the present inventive concept;

FIG. 2 is an enlarged diagram of part I of FIG. 1, FIGS. 3A and 3B arediagrams for illustrating a wetting angle of copper in a reflow state ona contact substrate;

FIG. 4 is a diagram for illustrating a semiconductor device according toother embodiments of the present inventive concept;

FIG. 5 is an enlarged diagram of part II of FIG. 4;

FIG. 6 is a diagram for illustrating a semiconductor device according tofurther embodiments of the present inventive concept;

FIG. 7 is a diagram for illustrating a semiconductor device according tostill further embodiments of the present inventive concept;

FIG. 8 is a layout view for illustrating a semiconductor deviceaccording to still yet another embodiment of the present inventiveconcept;

FIG. 9 is a cross-sectional view taken along line A-A of FIG. 8;

FIG. 10 is a cross-sectional view taken along line B-B of FIG. 8;

FIGS. 11 and 12 are diagrams for illustrating a semiconductor deviceaccording to still further embodiments of the present inventive concept;

FIGS. 13 to 16 are middle-stage diagrams for illustrating a method offabricating a semiconductor device according to some embodiments of thepresent inventive concept;

FIGS. 17 and 18 are middle-stage diagrams for illustrating a method offabricating a semiconductor device according to other embodiments of thepresent inventive concept;

FIG. 19 is a block diagram of a memory card including the semiconductordevices according to some embodiments of the present inventive concept;

FIG. 20 is a block diagram of an information processing system using thesemiconductor devices according to some embodiments of the presentinventive concept; and

FIG. 21 is a block diagram of an electronic apparatus includingsemiconductor devices according to sonic embodiments of the presentinventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Advantages and features of the present inventive concept and methods ofaccomplishing the same may be understood more readily by reference tothe following detailed description of preferred embodiments and theaccompanying drawings. The present inventive concept may, however, beembodied in many different forms and should not be construed as beinglimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete andwill fully convey the concept of the invention to those skilled in theart, and the present inventive concept will only be defined by theappended claims. Like reference numerals refer to like elementsthroughout the specification.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

It will be understood that when an element or layer is referred to asbeing “on”, “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on”, “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present As used herein, the term “and/or”includes any and ail combinations of one or more of the associatedlisted items.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, components, regions, layersand/or sections, these elements, components, regions, layers and/orsections should not be limited by these terms. These tern s are onlyused to distinguish one element, component, region, layer or sectionfrom another region, layer or section. Thus, a first element, component,region, layer or section discussed below could be termed a secondelement, component, region, layer or section without departing from theteachings of the present inventive concept.

Spatially relative terms, such as “beneath”, “below”, “lower”, “above”,“upper”, and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s)feature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features, Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

Embodiments are described herein with reference to cross-sectionillustrations that are schematic illustrations of idealized embodiments(and intermediate structures). As such, variations from the shapes ofthe illustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, these embodiments shouldnot be construed as limited to the particular shapes of regionsillustrated herein but are to include mean to targets in shapes thatresult, for example, from manufacturing. For example, an implantedregion illustrated as a rectangle will, typically, have rounded orcurved features and/or a gradient of implant concentration at its edgesrather than a binary change from implanted to non-implanted region.Likewise, a buried region formed by implantation may result in someimplantation in the region between the buried region and the surfacethrough which the implantation takes place. Thus, the regionsillustrated in the figures are schematic in nature sand their shapes arenot intended to illustrate the actual shape of a region of a device andare not intended to limit the scope of the present inventive concept. Asappreciated by the present inventive entity, devices and methods offorming devices according to various embodiments described herein may beembodied in microelectronic devices such as integrated circuits, whereina plurality of devices according to various embodiments described hereinare integrated in the same microelectronic device. Accordingly, thecross-sectional view(s) illustrated herein may be replicated in twodifferent directions, which need not be orthogonal, in themicroelectronic device. Thus, a plan view of the microelectronic devicethat embodies devices according to various embodiments described hereinmay include a plurality of the devices in an array and/or in atwo-dimensional pattern that is based on the functionality of themicroelectronic device.

The devices according to various, embodiments described herein may beinterspersed among other devices depending on the functionality of themicroelectronic device. Moreover, microelectronic devices according tovarious embodiments described herein may be replicated in a thirddirection that may be orthogonal to the two different directions, toprovide three-dimensional integrated circuits.

Accordingly, the cross-sectional view(s) illustrated herein providesupport for a plurality of devices according to various embodimentsdescribed herein that extend along two different directions in a planview and/or in three different directions in a perspective view. Forexample, when a single active region is illustrated in across-sectional, view of a device, structure, the device/structure mayinclude a plurality of active regions and transistor structures (ormemory cell structures, gate structures, etc., as appropriate to thecase) thereon, as would be illustrated by a plan view of thedevice/structure.

Unless otherwise defined, all terms including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which the present inventive conceptbelongs. It will be further understood that terms, such as those definedin commonly used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand this specification and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

Hereinafter, a semiconductor device according to an embodiment of thepresent inventive concept will be described with reference to FIGS. 1 to3B.

FIG. 1 is a diagram for illustrating a semiconductor device according tosonic embodiments of the present inventive concept. FIG. 2 is anenlarged diagram of part I of FIG. 1.

FIGS. 3A and 3B are diagrams for illustrating a wetting angle of copperin a reflow state on a contact substrate.

For reference, FIG. 3A illustrates a wetting angle of copper in a reflowstate on a contact substrate made of a material, included in a firstliner layer, and FIG. 3B illustrates the wetting angle of copper in thereflow state on a contact substrate made of a material included in afirst barrier layer.

Referring to FIGS. 1 and 2, a semiconductor device 1 according to someembodiments of the present inventive concept may include a firstinterlayer insulating layer 110, a first barrier layer 120, a firstliner layer 130, a first metal wire 140, and the like.

The first interlayer insulating layer 110 may be formed on a substrate100. The first interlayer insulating layer 110 may include a firsttrench 115 formed in the first interlayer insulating layer 110.

A first etch stop layer 105 may be further included between the firstinterlayer insulating layer 110 and the substrate 100. The first trench115 included in the first interlayer insulating layer 110 may extend upto the first etch stop layer 105.

The substrate 100 may be a structure in which a base substrate and anepitaxial layer are laminated, but is not limited thereto, The substrate100 may be a silicon substrate, a gallium-arsenic substrate, a silicongermanium substrate, a ceramic substrate, a quartz substrate, or adisplay glass substrate or a semiconductor on insulator (SOI) substrate.Hereinafter, the silicon substrate will be described as an example.Alternatively, the substrate 100 may have a form in which an insulatinglayer is formed on the silicon substrate.

Although not illustrated, the substrate 100 may include a conductivepattern. The conductive pattern may be a metal wire or a contact or mayalso be a gate electrode of a transistor, a source/drain of thetransistor, or a diode, but is not limited thereto.

The first etch stop layer 105 is formed on the substrate 100. The firstetch stop player 105 may include, for example, silicon nitride, siliconoxynitride, silicon carbon nitride, and the like.

The first interlayer Insulating layer 110 may include, for example, atleast one of silicon oxide, silicon nitride, silicon oxynitride, and alow dielectric material. The first interlayer insulating layer 110 mayinclude the low -dielectric material to reduce a coupling phenomenonbetween the wires.

The low dielectric material may include, for example, flowable oxide(FOX), tonen silazen (TOSZ), undoped silica glass (USG), borosilicaglass (BSG), phosphosilica glass (PSG), borophosphosilica glass (BPSG),plasma enhanced tetra ethyl ortho silicate (PETEOS), fluoride silicateglass (FSG), carbon doped silicon oxide (CDO), xerogel, aerogel,amorphous fluorinated carbon, organo silicate glass (OSG), parylene,bis-benzocyclobutenes (BCH), SILK, polyimide, porous polymeric material,or combinations thereof, but is not limited thereto.

The first barrier layer 120 may be formed along a side wall and a bottomsurface of the first trench 115. The first barrier layer 120 may preventor reduce the likelihood of an element included in the first metal wire140 from being diffused to the first interlayer insulating layer 110 orprevent or reduce the likelihood of oxygen included in the firstinterlayer insulating layer 110 from being diffused to the first linerlayer 130 and the first metal wire 140.

The first barrier layer 120 may include one of, for example, titanium(Ti), titanium nitride (TIN), tantalum (Ta), tantalum nitride (TaN),tantalum carbon nitride (TaCN), tungsten (W), tungsten nitride (WN),tungsten carbon nitride (WCN), zirconium (Zr), zirconium nitride (ZrN),vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride(NbN), and combinations thereof.

In the following description, the first harrier layer 120 includestantalum (Ta), but is not limited thereto.

The first liner layer 130 may be formed on the side wall and the bottomsurface of the first trench 115. The first liner layer 130 may be formedon the first barrier layer 120. That is, the first barrier layer 120 maybe formed between the first liner layer 130 and the first interlayerinsulating layer 110.

In the semiconductor device 1 according to some embodiments of thepresent inventive concept, the first liner layer 130 may be conformallyformed on the side wall and the bottom surface of the first trench 115.

The first liner layer 130 may include a material that has strongerresistance to a chemical material than the first metal wire 140. In moredetail, the first liner layer 130 may include a material that hasstronger chemical resistance to slurry used in a CMP process than thefirst metal wire 140.

The first liner layer 130 may include a noble metal that has, resistanceto corrosion, and oxidation under a humid environment. For example, thefirst liner layer 130 belongs to an eighth group to a tenth group, in aperiodic chart that follows IPUAC numbering of International Union ofPure and Applied Chemistry (IUPAC) and may be noble metal that belongsto a fifth period and/or a sixth period.

In detail, the first liner layer 130 may include, for example, at leastone of ruthenium (Ru), platinum (Pt), iridium (Ir), and a rhodium (Rh).That is, the noble metal may include, for example, at least one ofruthenium (Ru), platinum (Pt), iridium (Ir), and a rhodium (Rh).

In the following description, the first liner layer 130 is described asincluding ruthenium (Ru), but is not limited thereto.

The first metal wire 140 may be formed by filling the first trench 115.The first metal wire 140 may be formed on the first liner layer 130. Thefirst metal wire 140 may be electrically, connected with the conductivepattern, which may be included in the substrate 100.

The first metal wire 140 may include copper (Cu), which is high inconductivity and high in electromigration resistance. Further, thecopper included in the first metal wire 140 may include, for example,carbon (C), silver (Ag), cobalt (Co), tantalum (Ta). indium (In), tin(Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chrome(Cr), germanium (Ge), strontium (Sr), platinum (Pt), magnesium (Mg),aluminum (Al), or zirconium (Zr).

In the semiconductor device according to some embodiments of the presentinventive concept, a top surface 140 t of the first metal wire 140 maybe a curved surface having a convex shape toward the bottom surface ofthe first trench 115. The top surface 140 t of the first metal wire 140may be concave from a top surface 110 u of the first interlayerinsulating layer 110.

In more detail, the top surface 1401 of the first metal wire 140 mayinclude a first point P1 and a second point P2. A distance up to thefirst point P1 from a point at which the top surface 140 t of the firstmetal wire 140 and an uppermost surface 130 u of the first liner layer130 meet may be smaller than a distance up to the second point P2 fromthe point at which the top surface 140 t of the first metal wire 140 andthe uppermost surface 130 u of the first liner layer 130 meet.

In this case, a first depth dl up to the first point P1 from theuppermost surface 130 u of the first liner layer 130 is smaller than asecond depth d2 up to the second point P2 from the uppermost surface 130u of the first liner layer 130.

In other words, the center of the top surface 140 t of the first metalwire 140 is most recessed <based on the uppermost surface 130 u of thefirst liner layer 130 and the top surface 140 t of the first metal wire140 adjacent to the uppermost surface 130 u of the first liner layer 130may not be recessed based on the uppermost surface 130 u of the firstliner layer 130.

In the semiconductor device according to some embodiments of the presentinventive concept, the uppermost surface 130 u of the first liner layerand the top surface 140 t of the first metal wire 140 may be continuousat a point where the first liner layer 130 and the top surface 140 t ofthe first metal wire 140 are adjacent to each other.

In other words, a step may not be formed between the uppermost surface130 u of the first liner layer and the top surface 1401 of the firstmetal wire 140, at the point where the first liner layer 130 and the topsurface 140 t of the first metal wire 140 are adjacent to each other.

Accordingly, the uppermost surface 130 u of the first liner layer andthe top surface 140 t of the first metal wire 140 may directly contacteach other, at the point where the first liner layer 130 and the firstmetal wire 140 area adjacent to each other.

The top surface 140 t of the first metal wire 140 has a convex shapetoward the bottom surface of the first trench 115. And, the step is notformed between the uppermost surface 130 u of the first liner layer 130and the top surface 140 t of the first metal wire 140. So, the topsurface 140 t of the first metal wire 140 may not entirely protrudeabove the uppermost surface 130 u of the first liner layer 130.

Referring to FIGS. 3A and 3B, when the copper (Cu) included in the firstmetal wire 140 is in the reflow state, a wetting angle or a contactangle depending on types of contact substrates 121 and 131 will bedescribed.

The first contact substrate 131 of FIG. 3A may be a substrate made of anoble, metal included in the first liner layer 130 and the secondcontact substrate 121 of FIG. 3B may be a substrate made of a materialincluded in the first barrier layer 120.

Wetting shows a tendency of a material in a fluid state, which covers asolid surface. Wettability is determined by a balance between adhesiveforce between solid and fluid, which allows the fluid to be evenlydiffused, and cohesive force in the fluid.

That is, when the adhesive force between the solid and the fluid islarger than the cohesive force in the fluid, the fluid covers thesurface of the solid well. Therefore, a wetting characteristic of thefluid to the solid may be improved.

On the contrary, when the adhesive force between the solid and the fluidis smaller than the cohesive force in the fluid, the fluid does not wellcover the surface of the solid. Therefore, the wetting characteristic ofthe fluid to the solid may deteriorate.

In FIG. 3A, when first reflow copper 141 in the reflow state ispositioned on the first contact substrate 131, the first reflow copper141 has a first wetting angle θ1.

In FIG. 3B, when second reflow copper 142 in the reflow state ispositioned on the second contact substrate 121, the second reflow copper142 has a second wetting angle θ2. in this case, the first reflow copper141 and the second fellow copper 142 are substantially the same as eachother in other conditions except for the contact substrate.

In FIGS. 3A. and 3B, the first wetting angle θ1 is smaller than thesecond wetting angle θ2. For example, the first wetting angle θ1 may bean acute angle smaller than 90 degrees and the second wetting angle θ2may be an obtuse angle larger than 90 degrees.

That is, the copper in the reflow state is better wetted to the firstcontact substrate 131 made of the material included in the first linerlayer 130 than the second contact substrate 121 made of the materialincluded in the first barrier layer 120.

As the wetting characteristic is better, the fluid may be well diffusedon the surface of the solid. That is, during a fabrication process whenthe copper is in the reflow state having flexibility, the copper isbetter diffused on the first liner layer 130 than the, first barrierlayer 120.

If the first metal wire 140 is fabricated by using the reflow state inwhich the copper has the flexibility, when the copper in the reflowstate is faxed on the first liner layer 130 rather than on the firstbarrier layer 120, the copper in the reflow state may be betterdiffused. Accordingly, when the first metal wire 140 is formed by usingthe reflow process, the first metal wire 140 may be fabricated moreeasily on the first liner layer 130 than on, the first barrier layer120.

A semiconductor device according to other embodiments of the presentinventive concept will be described with reference to FIGS. 4 and 5. Foreasy description, a part duplicated with the embodiment described byusing FIGS. 1 and 2 will be described in brief or omitted.

FIG. 4 is a diagram for illustrating a semiconductor device according toother embodiments of the present inventive concept. FIG. 5 is anenlarged diagram of part of FIG. 4.

Referring to FIGS. 4 and 5, the semiconductor device 2 according toother embodiments of the present inventive concept may further include afirst capping layer 150.

The first capping layer 150 may be formed on the top surface 140 t ofthe first metal wire 140. The first capping layer 150 may be formedalong the top surface 140 t of the first metal wire 140.

The first capping layer 150 may directly contact the first metal wire140 and the first liner layer 130. The first capping layer 150 may coverthe top surface 140 t of the first metal wire 140 on the whole.

In the semiconductor device according to other embodiments of thepresent inventive concept, the first capping layer 150 is formed only onthe top surface 140 t of the first metal wire 140 and may not extendonto the uppermost surface 130 u of the first liner layer 130. Further,the first capping layer 150 may not extend onto an uppermost surface 120u of the first harrier layer and an uppermost surface of the firstinterlayer insulating layer 110.

In FIG. 5, the top surface 140 t of the first metal wire 140 and theuppermost surface 130 u of the first liner layer 130 do not directlycontact each other, and no step is formed between the top surface 140 tof the first metal wire 140 and the, uppermost surface 130 u of thefirst liner layer 130. A part of the first capping layer 150 formed onthe top surface 140 t of the first metal wire 140 may protrude above theuppermost surface 13 of the first liner layer 130, but is not limitedthereto.

The first capping layer 150 may be formed along the top surface 40 t ofthe first metal wire 140, and the first liner layer 130 may be formedalong a side wall 140 s and a bottom surface 140 b of the first metalwire 140. That is, the first capping layer 150 and the first liner layer130 may cover the first metal wire 140 on the whole.

The first capping layer 150 may include a material that may prevent orreduce the electromigration, which may occur along the top surface 140 tof the first metal wire when current flows on the first metal wire 140.The first capping layer 150 may include, for example, at least one ofcobalt (Co), ruthenium (Ru). and manganese (Mn).

A semiconductor device according to yet other embodiments of the presentinventive concept will be described with reference to FIG. 6. For easydescription, a part that is duplicated with the embodiments describedwith reference to FIGS. 4 and 5 will be described in brief or omitted.

FIG. 6 is a diagram for illustrating a semiconductor device according toyet other embodiments of the present inventive concept.

Referring to FIG. 6, in a semiconductor device 3 according to yet otherembodiments of the present inventive concept, the first capping layer150 may extend onto the uppermost surface 130 u of the first liner layerand the uppermost surface 120 u of the first barrier layer.

However, the first capping layer 150 does not extend onto the topsurface 110 u of the first interlayer insulating layer 110. The reasonis that a method of selectively forming a layer on a conductive materialis used for the first capping layer 150.

In the semiconductor device 3 according to yet other embodiments of thepresent inventive concept, the first capping layer 150 extends onto theuppermost surface 120 u of the first barrier layer, but the presentdisclosure is not limited thereto, The first capping layer 150 extendsonto the top surface 140 t of the first metal wire and the uppermostsurface 130 u of the first liner layer 130 and may not extend onto theuppermost surface 120 u of the first barrier layer, of course.

In FIG. 6, because the first capping layer 150 is formed even on theuppermost surface 130 u of the first'liner layer 130 and the uppermostsurface 120 u of the first barrier layer 120, a part of the firstcapping layer 150 may protrude above the uppermost surface 130 u of thefirst liner layer 130.

Because the first capping layer 150 extends onto the uppermost surface120 u of the first barrier layer 120, the first capping layer 150 maydirectly contact the first barrier layer 120. The first barrier layer120 may be formed along the first liner layer 130, which is formed alongthe side wall 140 s and the bottom surface 140 b of the first metalwire. Accordingly, the first capping layer 150 and the first barrierlayer 120 may cover the first metal wire 140 and the first liner layer130 on the whole.

A semiconductor device according to still other embodiments of thepresent inventive concept will be described with reference to FIG. 7.For easy description, a part duplicated with the embodiments describedwith respect to FIGS. 1 and 2 will be described in brief or omitted.

FIG. 7 is a diagram for illustrating a semiconductor, device accordingto still other embodiments of the present inventive concept.

Referring to FIG. 7, in a semiconductor device 4 according to stillother embodiments of the present inventive concept, a thickness t2 ofthe first liner layer 130 formed on the bottom surface of the firsttrench 115 may be larger than a thickness t1 of the first liner layer130 formed on the side wall of the first trench 115.

When the first liner layer 130 is formed by using a deposition method inwhich step-coverage is bad, for example, physical vapor deposition(PVD), the thickness of the first liner layer 130 formed on the bottomsurface of the first trench 115 may be larger than the thickness of thefirst liner layer 130 formed on the side wail of the first trench 115.

At a portion where the top surface 140 t of the first metal wire 140 andthe uppermost surface 130 u of the first liner layer 130 meet. the firstliner layer 130 formed on the side wall of the first trench 115 may havean overhang structure 135.

A semiconductor device according to still other embodiments of thepresent inventive concept will be described with reference to FIGS. 8 to10. For easy description, a part duplicated with the embodimentsdescribed with respect to FIGS. 4 and 5 will be described in brief oromitted.

FIG. 8 is a layout diagram for illustrating a semiconductor deviceaccording to still yet another embodiment of the present inventiveconcept. FIG. 9 is a cross-sectional view taken along line A-A of FIG.8. FIG. 10 is a cross-sectional view taken along line B-B of FIG. 8.

Referring to FIGS. 8 to 10, a semiconductor device 5 according to stillother embodiments of the present inventive concept may further include asecond interlayer insulating layer 210, a second barrier layer 220, asecond liner layer 230, a second metal wire 240, a second capping layer250, and the like.

The second interlayer insulating layer 210 may be formed on the firstinterlayer insulating layer 110 and the first metal wire 140. The secondinterlayer insulating layer 210 may include a second trench 215 formedin the second interlayer insulating layer 210.

A second etch stop layer 205 that protects the first metal wire 140 maybe further included between the first interlayer insulating layer 110and the second interlayer insulating layer 210. The second trench 215may extend up to the second etch stop layer 205.

in the semiconductor device 5 according to still other embodiments ofthe present inventive concept, the second trench 215 may expose thefirst capping layer 150 positioned, below the second interlayerinsulating layer 210.

The second etch stop layer 205 is fanned on the first interlayerinsulating layer 110. The second etch stop layer 205 may include, forexample, silicon nitride, silicon oxynitride, silicon carbon nitride,and the like.

The second interlayer insulating layer 210 may include, for example, atleast one of silicon oxide, silicon nitride, silicon oxynitride, and thelow dielectric constant material. The second interlayer insulating layer210 may include a low-dielectric material to reduce the couplingphenomenon between the wires, like the first interlayer insulating layer110.

The second barrier layer 220 may be formed along a side wail and abottom surface of the second trench 215. In the semiconductor device 5according to still other embodiments of the present inventive concept,the second barrier layer 220 may be formed along a profile of the firstcapping layer 150 exposed by the second trench 215. The second barrierlayer 220 may directly contact the first capping layer 150, but may notdirectly contact the first metal wire 140.

The second barrier layer 220 may include, for example, one of titanium(Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN),tantalum carbon nitride (TaCN), tungsten (W), tungsten nitride (WN),tungsten carbon nitride (WCN), zirconium (Zr), zirconium nitride (ZrN),vanadium (V), vanadium nitride (VN), niobium (Nb). niobium nitride(NbN), and combinations thereof.

The second liner layer 230 may be formed along the side wall and thebottom surface of the second trench 215. The second liner layer 230 maybe formed on the second barrier layer 220. That is, the second barrierlayer 220 may be formed between the second liner layer 230 and thesecond interlayer insulating layer 210.

The second liner layer 230 may include a noble metal, which hasresistance to corrosion and oxidation under a humid environment. Forexample, the second liner layer 230 belongs to the eighth group to thetenth group, in the periodic chart that follows IPUAC numbering ofInternational Union of Pure and Applied Chemistry (IUPAC) and may be anoble metal that belongs to the fifth period and/or the sixth period.

In detail, the second liner layer 230 may include, for example, at leastone of ruthenium (Ru), platinum (Pt), iridium (Ir), and rhodium (Rh).

For example, the first metal wire 140 may extend in a first direction Xand the second metal. wire 240 may extend, in a second direction Y. Thesecond metal wire 240 may be formed on the first metal wire 140.

The second metal wire 240 may be formed by filling the second trench215, in the second trench 215. The second metal wire 240 may be formedon the second liner layer 230.

The second metal wire 240 may include a via portion 240 v that contactsthe first capping layer 150 and a wire portion 240 w that extends in thesecond direction Y. The wire portion 240 w of the second metal wire maybe connected with the first metal wire 140 via the via portion 240 v ofthe second metal wire.

In the semiconductor device 5 according to still other embodiments ofthe present inventive concept, the first capping layer 150, the secondbarrier layer 220, and the second liner layer 230 may be positionedbetween a bottom surface of the via portion 240 v of the second metalwire and the top surface 140 i of the first metal wire.

The second metal wire 240 may include copper (Cu). Further, the copperincluded in the second metal wire 240 may include, for example, carbon(C), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn),zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chrome (Cr),germanium (Ge), strontium (Sr), platinum (Pt), magnesium (Mg), aluminum(Al), or zirconium (Zr).

In the semiconductor device 5 according to still other embodiments ofthe present inventive concept, a top surface 240 t of the second metalwire 240 may be a curved surface having a convex shape toward the bottomsurface of the second trench 215. The top surface 240 t of the secondmetal wire 240 may be concave from a top surface of the secondinterlayer insulating layer 210.

In FIGS. 8 to 10, the top surface 140 t of the first metal wire 140having the convex shape toward the bottom surface of the first trench115 may extend in the first direction X, and the top surface 240 t ofthe second metal wire 240 having the convex shape toward the bottomsurface of the second trench 215 may extend in the second direction Y.That is, the top surface 140 t of the first metal wire 140 and the topsurface 240 t of the second metal wire 240 may have a half-pipe shape.

At a point where the second liner layer 230 and the top surface 240 t ofthe second metal wire 240 are adjacent to each other, an uppermostsurface of the second liner layer 230 and the top surface 240 t of thesecond metal wire 240 may be continuous. In other words, at the pointwhere the second liner layer 230 and the top surface 24′0 of the secondmetal wire 240 are adjacent to each other, no step may be formed betweenthe uppermost surface of the second liner layer 230 and the top surface240 t of the second metal wire 240.

The second capping layer 250 may be formed on the top surface 240 t ofthe second metal wire 240. The second capping layer 250 may be formedalong the top surface 240 t of the second metal wire 240.

The second capping layer 250 may directly contact the second metal wire240 and the second liner layer 230. The second capping layer 250 maycover the top surface 240 t of the second metal wire on the whole.

The second capping layer 250 may include, for example, at least one ofcobalt (co), ruthenium (Ru), and manganese (Mn).

The second capping layer 250 may, be formed along the top surface 240 tof the second metal wire 240, and the second liner layer 230 may beformed along the side wall and the bottom surface of the second metalwire 240. That is, like the case where the first capping layer 150 andthe first liner layer 130 covers the first metal wire 140 on the whole,the second capping layer 250 and the second liner layer 230 may coverthe second metal wire 240 on the whole.

A semiconductor device according to still other embodiments of thepresent inventive concept will be described with reference to FIGS. 8,11, and 12. For easy description, a part duplicated with the embodimentsdescribed with reference to FIGS. 9 and 10 will be described in brief oromitted.

FIGS. 11 and 12 are diagrams for illustrating a method for fabricating asemiconductor device according to still other embodiments of the presentinventive concept. For reference, FIG. 11 is a cross-sectional viewtaken along line A-A of FIG. 8 and FIG. 12 is a cross-sectional viewtaken along line B-B of FIG. 8.

Referring to FIGS. 11 and 12, in a semiconductor device 6 according tostill other embodiments of the present inventive concept, the firstcapping layer 150 may include an opening 150 h that exposes a part ofthe top surface 140 t of the first metal wire 140.

The position of the opening 150 h included in the first capping layer150 may correspond to a position where the via portion 240 v of thesecond metal wire 240 is formed. That is, the first capping layer 150may cover the top surface 140 t of the first metal wire 140 on thewhole, except for the position where the via portion 240 v of the secondmetal wire 240 is formed.

Because the top surface 140 t of the first metal wire 140 is exposed bythe opening 150 h, the second barrier layer 220 may directly contact thefirst metal wire 140, Further, the second barrier layer 220 formed onthe bottom surface of the second trench 215 may formed along a profileof the top surface 1401 of the first metal wire 140.

In the semiconductor device 6 according to still other embodiments ofthe present inventive concept, the first capping layer 150 and the firstliner layer 130 may cover the first metal wire 140 on the whole, exceptfor the portion exposed by the opening 150 h.

A method of fabricating a semiconductor device according to someembodiments of the present inventive concept will be described withreference to FIGS. 1, 4, 13 to 16. The semiconductor device fabricatedthrough the method may be the semiconductor device described withrespect to FIG. 4.

FIGS. 13 to 16 are middle-stage diagrams for illustrating a method forfabricating a semiconductor device according to some embodiments of thepresent inventive concept.

Referring to FIG. 13, the first etch stop layer 105 and the firstinterlayer insulating layer 110 are sequentially formed on the substrate100.

The first etch stop layer 105 may be formed through, for example.chemical vapor deposition (CVD), and the like.

The first interlayer insulating layer 110 may be formed by using, forexample, CVD, spin coating, plasma enhanced CVD (PECVD), high densityplasma CVD (HDP-CVD), and the like.

Subsequently, the first trench 115 may be formed in the first interlayerinsulating layer 110 and the first etch stop layer 105 by etching thefirst interlayer insulating layer 110 and the first etch stop layer 105by using a mask pattern and the like. Therefore, the first interlayerinsulating layer 110 including the first trench 115 may be formed on thesubstrate 100.

Referring to FIG, 14, a prebarrier layer 120P and a preliner layer 130Fmay he sequentially formed along the side wall and the bottom surface ofthe first trench 115 and the top surface 110 u of the first interlayerinsulating layer.

The prebarrier layer 120P may include, for example, one of titanium(Ti), titanium nitride (TIN), tantalum (Ta), tantalum nitride (TaN),tantalum carbon nitride (TaCN), tungsten (W), tungsten nitride (WN),tungsten carbon nitride (WCN), zirconium (Zr), zirconium nitride (ZrN),vanadium (V), vanadium nitride (VN), niobium (Nb). niobium nitride(NbN), and combinations thereof. The prebarrier layer 120P may be formedby using, for example, methods including PVD, sputtering, CVD, atomiclayer deposition (ALD), and the like, but is not limited thereto.

The preliner layer 130P may include, for example, at least one ofruthenium (Ru), platinum (Pt), iridium (Ir), and rhodium (Rh), which arenoble metals. The preliner layer 130P may be formed by using, forexample, the methods including PVD, CVD, ALD, and the like, but is notlimited thereto. In the method of fabricating the semiconductor deviceaccording to some embodiments of the present inventive concept, it isdescribed that the preliner layer 130P is formed by using CVD.

Referring to FIG. 15, a pre-metal layer 140P-1 may be formed on thepreliner layer 130P, The pre-metal layer 140P-1 may fill a part of thefirst trench 115 and be formed on the top surface 110 u of the firstinterlayer insulating layer.

The pre-metal layer 140P-1 may include, for example, copper (Cu), Thepre-metal layer 140P-1 may be formed by using a method such as PVD orsputtering, but is not limited thereto.

Referring to FIG. 16, the pre-metal layer 140P-1 reflows by using areflow process 10 to form a metal layer 140P on the preliner layer 130P.

The metal layer 140 may fill the first trench 115. Further, the metallayer 140P may cover the top surface 110 u of the first interlayerinsulating layer 110.

Referring to FIG. 16, the metal layer 140P, the preliner layer 130P, andthe prebarrier layer 120P formed on the top surface 110 u of the firstinterlayer insulating layer 110 may be removed by using a planarizationprocess.

Therefore, the top surface 110 u of the first interlayer insulatinglayer may be, exposed. Further, the first barrier layer 120 and thefirst liner layer 130 may be formed along the side wail and the bottomsurface of the first trench 115, and the, first metal wire 140 may beformed, which fills the first trench 115.

A planarization process, for example, a chemical mechanical polishingprocess may be used.

A material included in the preliner layer 130P may be a noble metal andthe preliner layer 130P may have chemical resistance by slurry used inthe CMP process. That is, the preliner layer 130P may be removed by achemical polishing operation and a mechanical polishing operationdepending on the slurry, but the chemical polishing operation may belimitative.

However, the metal layer 140P may not have a chemical resistance by theslurry used in the CMP process. Accordingly, the metal layer 140P may beremoved by the chemical polishing operation and the mechanical polishingoperation, and may be removed more rapidly than the preliner layer 130P.

When the CMP process for forming the first metal wire 140P progresses,the top surface 140 t of the first metal wire adjacent to the firstliner layer 130 is polished less, and the center of the top surface 140t of the first metal wire distant from the first liner layer 130 ispolished more.

As a result, the top surface 140 t of the first metal wire may have aconvex shape toward the bottom surface of the first trench 115. Further,the top surface 140 t of the first metal wire and the uppermost surface130 u of the first liner layer are continuous, and no step may be formedbetween the top surface 1401 of the first metal wire and. the uppermostsurface 130 u of the first liner layer 130.

Subsequently, referring to FIG. 4, the first capping layer 150 may beformed on the top surface 140 t of the first metal wire.

The first capping layer 150 may be formed by using a method that mayselectively deposit the conductive material on the top surface 140 t ofthe first metal wire 140. Accordingly, the first capping layer 150 maynot extend onto the top surface 110 u of the first interlayer insulatinglayer 110.

A method of fabricating a semiconductor device according to otherembodiments of the present inventive concept will be described withreference to FIGS. 13, 14, 17, and 18.

FIGS. 17 and 18 are middle-stage diagrams for illustrating a method offabricating a semiconductor device according to other embodiments of thepresent inventive concept.

Referring to FIG. 17, a metal seed layer 140P-2 may be formed on thepreliner layer 130P. The metal seed layer 140P-2 may be formed on theside wall and the bottom surface of the first trench 115 and the topsurface 110 u of the first interlayer insulating layer 110.

The metal seed layer 140P-2 may include, for example, copper (Cu). Themetal seed layer 140P-2 may be formed by using the method such as thePVD or the sputtering. Alternatively, the metal seed layer 40P-2 may beformed by being immersed in an electrolyte including copper (Cu) ions.

Referring to FIG. 18, the metal layer 140P may be formed by using anelectroplating method.

The metal layer 140P may fill the first trench 115. Further, the metallayer 140P may cover the top surface 110 u of the first interlayerinsulating layer 110.

FIG. 19 is a block diagram of a memory card including a semiconductordevice according to some embodiments of the present inventive concept.

Referring to FIG. 19, a memory 1210 including a semiconductor deviceaccording to various embodiments of the present inventive concept may beadopted in a memory card 1200. The memory card 1200 may include a memorycontroller 1220 that controls data exchange between a host 1230 and thememory 1210. An SRAM 1221 may be used as an operating memory of acentral processing unit 1222. A host interface 1223 may include aprotocol for the host 1230 to exchange data by accessing the memory card1200. An error correction code 1224 may detect and correct an error ofdata read from the memory 1210. The memory interface 1225 may interfacewith the memory 1210. The central processing unit 1222 may perform anoverall control operation associated with the data exchange of thememory controller 1220.

FIG. 20 is a block diagram of an information processing system using asemiconductor device according to some embodiments of the presentinventive concept.

Referring to FIG. 20, the information processing system 1300 may includea memory system 1310 including a semiconductor device according tovarious embodiments of the present inventive concept. The informationprocessing system 1300 may include the memory system 1310, a modem 1320,a central processing unit 1330, a RAM 1340, and a user interface 1350,which are electrically connected with a system bus 1360. The memorysystem 1310 may include a memory 1311 and a memory controller 1312 andmay have the substantially same configuration as the memory cardillustrated in FIG. 19. Data processed by the central processing unit1330 or data received from an external device may be stored in thememory system 1310. The information processing system 1300 may beapplied to a memory card, an SSD, a camera image sensor, and variousother chipsets. For example, the memory system 1310 may be configured insuch a manner that the SSD is adopted, and in this case, the informationprocessing system 1300 may stably and. reliably process large-capacitydata.

FIG. 21 is a block diagram of an electronic apparatus including asemiconductor device according to some embodiments of the presentinventive concept.

Referring to FIG. 21, an electronic apparatus 1400 may include asemiconductor device according to various embodiments of the presentinventive concept. The electronic apparatus 1400 may be used in wirelesscommunication apparatuses (for example, a PDA, a notebook, a portablecomputer, a web tablet, a wireless phone, and/or a wireless digitalmusic player) or various apparatuses that transmit and receiveinformation under a wireless communication environment.

The electronic apparatus 1400 may include a controller 1410, aninput/output device 1420, a memory 1430, and a wireless interface 1440.Herein, the memory 1430 may include a semiconductor device according tovarious embodiments of the present inventive concept. The controller1410 may include a microprocessor, a digital signal processor, or aprocessor similar thereto. The memory 1430 may be used to store,commands (alternatively, user data) processed by the controller 1410.The wireless interface 1440 may be used to transmit and receive datathrough a wireless data network. The wireless interface 1440 may includean antenna and/or a wireless transceiver. The electronic apparatus 1400may use 3rd-generation communication system protocols such as CDMA. GSM,NADC, E-TDMA, WCDMA, and CD NIA 2000.

The foregoing is illustrative of the present inventive concept and isnot to be construed as limiting thereof. Although a few embodiments ofthe present inventive concept have been described, those skilled in theart will readily appreciate that many modifications are possible in theembodiments without materially departing from the novel teachings andadvantages of the present inventive concept. Accordingly, all suchmodifications are intended to be included within the scope of thepresent inventive concept as defined in the claims. Therefore, it is tobe understood that the foregoing is illustrative of the presentinventive concept and is not to be construed as limited to the specificembodiments disclosed, and that modifications to the disclosedembodiments, as well as other embodiments, are intended to be includedwithin the scope of the appended claims. The present inventive conceptis defined by the following claims, with equivalents of the claims to beincluded therein.

What is claimed is:
 1. A semiconductor device, comprising: a firstinterlayer insulating layer including a first trench, on a substrate; afirst liner layer along a side wall and a bottom surface of the firsttrench and including a noble metal, the noble metal belonging to one ofa fifth period and a sixth period of a periodic chart that followsnumbering of International Union of Pure and Applied Chemistry (IUPAC)and belonging to one of eighth to tenth groups of the periodic chart; afirst metal wire filling the first trench on the first liner layer, atop surface of the first metal wire having a convex shape toward abottom surface of the first trench; and a capping layer on the topsurface of the first metal wire.
 2. The semiconductor device of claim 1,wherein at a point where the first liner layer and the top surface ofthe first metal wire are adjacent to each other, an uppermost surface ofthe first iffier layer and the top surface of the first metal wire arecontinuous.
 3. The semiconductor device of claim 2, wherein at the pointwhere the first liner layer and the top surface of the first metal wireare adjacent to each other, no step is between the uppermost surface ofthe first liner layer and the top surface of the first metal wire. 4.The semiconductor device of claim 1, wherein the top surface of thefirst metal wire comprises a first point and a second point, a distanceup to the first point from a point where the top surface of the firstmetal wire and an uppermost surface of the first liner layer meet isless than a distance up to the second point from the point where the topsurface of the first metal wire and the uppermost surface of the firstliner layer meet, and a depth up to the first point from the uppermostsurface of the first liner layer is less than a depth up to the. secondpoint front the uppermost surface of the first liner layer.
 5. Thesemiconductor device of Claim 1, wherein the noble metal comprises atleast one of ruthenium (Ru) platinum (Pt), iridium (Ir), and rhodium(Rh).
 6. The semiconductor device of claim 1, wherein the capping layerdirectly contacts the first liner layer and the first metal wire.
 7. Thesemiconductor device of claim 1, wherein the capping layer does notextend on the top surface of the first interlayer insulating layer. 8.The semiconductor device of claim 1, wherein the capping layer comprisesat least, one of cobalt (Co), ruthenium (Ru), and manganese (Mn).
 9. Thesemiconductor device of claim 1, further comprising: a first barrierlayer along the side wall and the bottom surface of the first trench,between the first interlayer insulating layer and the first liner layer.10. The semiconductor device of claim 9, wherein the first barrier layeris directly on an upper surface of the substrate.
 11. The conductordevice of claim 10, further comprising: an etch stop layer between thefirst interlayer insulating layer and the substrate.
 12. Thesemiconductor device of claim 11, wherein the etch stop layer isdirectly on the upper surface of the substrate.
 13. The semiconductordevice of claim 1, further comprising: a second interlayer insulatinglayer comprising a second trench, on the first interlayer insulatinglayer; a second liner layer along a side wall and a bottom surface ofthe second trench and including the noble metal; and a second metal wirefilling the second trench and electrically connected with the firstmetal wire, wherein a top surface of the second metal wire has a convexshape toward the bottom surface of the second trench.
 14. Asemiconductor device, comprising: an interlayer insulating layercomprising a trench, on a substrate; a barrier layer along a side walland a bottom surface of the trench; a ruthenium (Ru) liner layer alongthe side wall and the bottom surface of the trench, on the barrierlayer; a metal wire filling the trench and comprising copper, on theruthenium liner layer, a top surface of the metal wire having a convexshape toward the bottom surface of the trench and being continuous withan uppermost surface of the ruthenium liner layer; and a capping layeralong the top surface of the metal wire.
 15. The semiconductor device ofclaim 14, wherein the metal wire directly contacts the ruthenium linerlayer, and wherein no step is between the uppermost surface of theruthenium, liner layer and the top surface of the metal wire.
 16. Thesemiconductor device of claim 14, wherein the capping layer is a cobalt(Co) layer.
 17. The semiconductor device of claim 14, wherein theinterlayer insulating layer comprises a low-dielectric material having alower dielectric constant than silicon oxide.
 18. A semiconductor devicecomprising: a substrate; an insulating layer, having a trench therein,on the substrate; a metal liner layer in the trench; a metal wire in thetrench on the metal liner layer; and a metal capping layer on the metalwire. wherein a combination of the metal capping layer and the metalliner layer covers four surfaces of the metal wire.
 19. Thesemiconductor device of claim 18, wherein the four surfaces of the metalwire comprise a bottom surface, first and second side surfaces, and anon-planar top surface, wherein a non-planar portion of the metalcapping layer covers the non-planar top surface of the metal wire, andwherein the metal liner layer covers the bottom surface of the metalwire, and the first and second side surfaces of the metal wire.
 20. Thesemiconductor device of claim 19, further comprising a metal barrierlayer in the trench, wherein the metal liner layer is between the metalbarrier layer and the metal wire.